1. Field of the Invention
This invention generally relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) and reducing the line width of the gate structure.
2. Description of Related Art
As the integration level of integrated circuits increases, the semiconductor devices are getting smaller and smaller. MOSFETs become the widely used devices in the integrated circuits because of their low power consumption and suitability for high-density integrated circuits. To overcome the problems of a higher contact resistance, a longer RC delay, and a lower operational speed due to the diminution of the line width of the gate, conventionally, a metal silicide is formed on the gate to reduce the resistance between the gate and the metal line.
However, as the line width of the gate continues to shrink, it is more difficult to form the desired line width because the photolithography process is much more difficult to control, which will affect the design rule margin.
Further, when the line width of the gate shrinks to below a particular size, a line width effect occurs so that the metal silicide layer can not be well formed on the gate structure with a smaller line width.
In addition, the profile of the extension of the drain and the source also becomes smaller and smaller as the device continues to shrink. Hence, the extension of the drain and the source has to sustain the thermal budget of the anneal process for the metal silicide layer, which makes the profile of the extension of the drain and the source difficult to control.
An object of the present invention is to provide a method for fabricating a MOSFET and reducing the line width of the gate, wherein a larger design rule margin is provided for photolithography processes for defining the line width of the gate structure.
Another object of the present invention is to provide a method for fabricating a MOSFET and reducing the line width of the gate, wherein the line width effect of the metal silicide layer is avoided and a metal silicide layer of good quality is formed on the gate structure.
Still another object of the present invention is to provide a method for fabricating a MOSFET to reduce the annealing temperature at the extension of the drain and the source so that the profile of the extension of the drain and the source can be controlled.
The present invention provides a method for fabricating a MOSFET, comprising: providing a substrate, the substrate having a gate structure; forming a drain region and a source region in the substrate, the drain region and the source region being on two sides of the gate structure respectively; forming a metal silicide layer on the surface of the gate structure, the drain region, and the source region; forming a patterned block on the metal silicide layer above the gate structure, and forming a first dielectric layer above the substrate except the metal silicide layer, the patterned block being formed above the center of the gate structure and the metal silicide layer above the gate structure and not covered by the patterned block being exposed on two sides of the patterned block; removing a portion of the metal suicide layer and a portion of the gate structure by using the patterned block as a mask; and forming a drain extension region and a source extension region in the substrate, the drain extension region and the source extension region being on two sides of the remaining gate structure.
In a preferred embodiment of the present invention, the step of forming the patterned block and the first dielectric layer includes performing high density plasma chemical vapor deposition (HDPCVD).
In a preferred embodiment of the present invention, the metal suicide layer exposed on the one side of the patterned block and on the other side of the patterned block are symmetrical and have a same area.
The present invention provides a method for reducing the line width of a gate, comprising: providing a substrate, the substrate having a gate structure; forming a patterned block on the gate structure with high density plasma chemical vapor deposition, the patterned block being formed on the center of the gate structure, the gate structure not covered by the patterned block being exposed on two sides of the patterned block; and removing a portion of the gate structure by using the patterned block as a mask.
In a preferred embodiment of the present invention, the gate structure exposed on the one side of the patterned block and on the other side of the patterned block are symmetrical and have a same area.
In brief, the present invention reduces the line width of the gate structure by forming a patterned block on the gate structure. Hence, the line width of the gate structure can be defined during the photolithography process to be wider so that the photolithography process has a larger design rule margin.
Further, because the present invention provides a larger line width for the gate structure, the metal silicide layer can be well formed on the gate structure without the line width effect.
In addition, because the extension of the drain and the source is formed after the metal silicide layer is formed, the extension of the drain and the source does not have to sustain the thermal budget of the anneal process for forming the metal silicide layer. Hence, the profile of the extension of the drain and the source is easier to control.
The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.